1. Field of the Invention
The present invention relates to a level interface circuit that can cope with different interface inputs standards and reference levels.
2. Related Arts
LVTTL (Low Voltage Transistor Transistor Logic) circuits have been widely employed as interfaces for dynamic RAM and other integrated circuit devices. A LVTTL circuit has a low TTL voltage level that requires a power voltage of 3.3 V, which is slightly lower than the TTL power voltage level of 5 V. According to its specifications, the voltage of a LVTTL must be 2.0 V or higher at level H, and 0.8 V or lower at level L, with the reference level Vref being fixed at a middle voltage of 1.4 V. Since the bus of a system is open ended, one failing of a LVTTL circuit is that the production of noise due to ringing is increased during a high-speed operation.
An SSTL (Series Stub Termination Logic) circuit has been proposed as an interface that is suitable for high-speed operation. According to the specifications for the use of the SSTL, the bus of a system is closed using a predetermined resistance to prevent the production of noise during a high-speed operation. For the SSTL circuit, the reference level Vref is around 0.45 times (0.43 to 0.47 times) the power voltage Vcc, and fluctuates in accordance with changes in the power voltage. The level H for a signal is set 0.2 V higher than the reference level Vref, and the level L is set 0.2 V lower than the reference level Vref.
FIG. 8 is a diagram showing the relationship between the levels of the LVTTL and SSTL interface circuits. For the LVTTL circuit, as is described above, the reference level Vref is set about 1.4 V higher than the ground Vss, regardless of the power voltage Vcc, and is ordinarily generated in an integrated circuit. For the SSTL circuit, the reference level Vref varies in accordance with changes in the power voltage Vcc, and is externally supplied to an integrated circuit. It should be noted that for the SSTL circuit the entire system bus is a platform whereat the reference level voltage Vref and the level of the signal vary as the power voltage Vcc fluctuates, and strongly resists changes in the power voltage.
FIG. 7 is a diagram illustrating a conventional level interface circuit. This circuit includes N type transistors Q1 and Q2, to which input signal IN and reference voltage level Vref are supplied at their respective gates; a current source transistor Q3, which is provided between a common source terminal ns and a ground Vss and is controlled by an enable signal EN; and a load circuit having P type transistors P1 and P2, which are located between the drains of the transistors Q1 and Q2 and an internal power source Vii. The load circuit is a current mirror circuit for adjusting the current values on either side to values proportional to the areas of the transistors P1 and P2. The internal power voltage Vii is a low voltage generated by the power source Vcc, and has a fixed potential which is not affected by changes in the power voltage Vcc. The output terminal OUT is connected to the drain of the transistor Q1, and is transmitted to a CMOS circuit (not shown) at the following stage.
The level interface circuit compares externally input signal IN with the reference level voltage Vref, and in accordance with level H and level L of the input IN, generates at the output terminal OUT a signal whose level is adjusted to the level of a CMOS circuit at the following stage.
When the above described level interface circuit is designed while adjusting it to a LVTTL circuit, for example, a satisfactory operating margin can not be provided for the input signal IN and the reference level voltage Vref of the SSTL.
Assume that the power voltage Vii is supplied to the sources of the P type transistors P1 and P2, as is shown in FIG. 7. When the reference level voltage Vref and the input signal IN corresponding to the LVTTL circuit are supplied to the gates of the transistors Q1 and Q2, a normal operation is performed. But in case that the reference level voltage Vref and the input signal IN corresponding to the SSTL circuit are supplied to the gates of the transistors Q1 and Q2, when both the reference level voltage Vref (=Vcc.times.0.45) and the input signal IN rise as the power voltage Vcc is increased, as a result, the gate voltage goes too high relative to the common source node ns, and the transistors Q1 and Q2 may be rendered active in the saturated area. Thus, a signal at the out signal OUT does not have a sufficient amplitude, and a normal differential circuit operation is impossible. Where the power voltage Vcc falls, and accordingly, the reference level voltage Vref (=Vcc.times.0.45) and the input signal IN are dropped, the gate voltage goes too low relative to the common source node ns, and the transistors Q1 and Q2 may be rendered to be a less conductive area. In this case, a signal having an appropriate amplitude can not be generated at the output terminal OUT.
As is described above, it is difficult for the above described differential circuit to be applied under both a LVTTL interface, which does not depend on a power voltage, and an SSTL interface, which has a level which depends on a power voltage.